| Field Name | Bits | Type | Reset Value | Description |
|---|
| addr_decode_err | 31 | wtcReadable, write a 1 to clear | 0x0 | Address Decode Error |
| Reserved | 30:6 | roRead-only | 0x0 | Reserved |
| ccnt_oflw | 5 | wtcReadable, write a 1 to clear | 0x0 | Cycle Counter overflow |
| ec3_oflw | 4 | wtcReadable, write a 1 to clear | 0x0 | Event Counter 3 overflow |
| ec2_oflw | 3 | wtcReadable, write a 1 to clear | 0x0 | Event Counter 2 overflow |
| ec1_oflw | 2 | wtcReadable, write a 1 to clear | 0x0 | Event Counter 1 overflow |
| ec0_oflw | 1 | wtcReadable, write a 1 to clear | 0x0 | Event Counter 0 overflow |
| errorirq | 0 | wtcReadable, write a 1 to clear | 0x0 | Indicates that an error response, DECERR or SLVERR, has been received on the RREST or BRESP inputs, that cannot be signalled precisely |