ISR_1 (AMS) Register Description
Register Name | ISR_1 |
Offset Address | 0x0000000014 |
Absolute Address |
0x00FFA50014 (AMS_CTRL)
|
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Alarm and Access Error Interrupt Status and Clear, Reg 1. |
PS and PL over temperature, configuration finish and conversion finish. READ: 0: no event. 1: event asserted. WRITE: 0: no effect. 1: clear bit to 0. See ISR_0 for an additional description.
ISR_1 (AMS) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
addr_decode_err | 31 | wtcReadable, write a 1 to clear | 0x0 | AMS_CTRL Register Access Error. |
addr_decode_err_pl_sysmon | 30 | wtcReadable, write a 1 to clear | 0x0 | PLSYSMON Register Access Error. |
addr_decode_err_ps_sysmon | 29 | wtcReadable, write a 1 to clear | 0x0 | PSSYSMON Register Access Error. |
Reserved | 28:5 | roRead-only | 0x0 | reserved |
eos | 4 | wtcReadable, write a 1 to clear | 0x0 | PS SysMon End-of-Sequence (EOS). |
eoc | 3 | wtcReadable, write a 1 to clear | 0x0 | PS SysMon End-of-Conversion (EOC). |
pl_ot | 2 | wtcReadable, write a 1 to clear | 0x0 | PL over-temperature (OT) alarm. |
ps_lpd_ot | 1 | wtcReadable, write a 1 to clear | 0x0 | LPD over-temperature (OT) alarm. |
ps_fpd_ot | 0 | wtcReadable, write a 1 to clear | 0x0 | FPD over-temperature (OT) alarm. |