ISR_1 (AMS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ISR_1 (AMS) Register Description

Register NameISR_1
Offset Address0x0000000014
Absolute Address 0x00FFA50014 (AMS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAlarm and Access Error Interrupt Status and Clear, Reg 1.

PS and PL over temperature, configuration finish and conversion finish. READ: 0: no event. 1: event asserted. WRITE: 0: no effect. 1: clear bit to 0. See ISR_0 for an additional description.

ISR_1 (AMS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addr_decode_err31wtcReadable, write a 1 to clear0x0AMS_CTRL Register Access Error.
addr_decode_err_pl_sysmon30wtcReadable, write a 1 to clear0x0PLSYSMON Register Access Error.
addr_decode_err_ps_sysmon29wtcReadable, write a 1 to clear0x0PSSYSMON Register Access Error.
Reserved28:5roRead-only0x0reserved
eos 4wtcReadable, write a 1 to clear0x0PS SysMon End-of-Sequence (EOS).
eoc 3wtcReadable, write a 1 to clear0x0PS SysMon End-of-Conversion (EOC).
pl_ot 2wtcReadable, write a 1 to clear0x0PL over-temperature (OT) alarm.
ps_lpd_ot 1wtcReadable, write a 1 to clear0x0LPD over-temperature (OT) alarm.
ps_fpd_ot 0wtcReadable, write a 1 to clear0x0FPD over-temperature (OT) alarm.