ITATBCTR2 (ETR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ITATBCTR2 (ETR) Register Description

Register NameITATBCTR2
Offset Address0x0000000EF0
Absolute Address 0x00FE970EF0 (CORESIGHT_SOC_ETR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionThe Integration Test ATB Control Register 2 enables control of the ATREADYS and AFVALIDS outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior.

ITATBCTR2 (ETR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SYNCREQS 2woWrite-only0x0Set the value of SYNCREQS output
AFVALIDS 1woWrite-only0x0Set the value of AFVALIDS output
ATREADYS 0woWrite-only0x0Set the value of ATREADYS output