ITATBMCTR1 (ETR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ITATBMCTR1 (ETR) Register Description

Register NameITATBMCTR1
Offset Address0x0000000ED8
Absolute Address 0x00FE970ED8 (CORESIGHT_SOC_ETR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionThe Integration Test ATB Master Control Register 1 enables control of the ATIDM outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior.

ITATBMCTR1 (ETR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ATIDM 6:0woWrite-only0x0Control the value of ATIDM output from TMC. The value written to this field is driven on the ATIDM output of the TMC.