ITATBMCTR1 (ETR) Register Description
Register Name | ITATBMCTR1 |
---|---|
Offset Address | 0x0000000ED8 |
Absolute Address | 0x00FE970ED8 (CORESIGHT_SOC_ETR) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | The Integration Test ATB Master Control Register 1 enables control of the ATIDM outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
ITATBMCTR1 (ETR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ATIDM | 6:0 | woWrite-only | 0x0 | Control the value of ATIDM output from TMC. The value written to this field is driven on the ATIDM output of the TMC. |