ITATBMDATA0 (ETF4K) Register Description
| Register Name | ITATBMDATA0 |
|---|---|
| Offset Address | 0x0000000ED0 |
| Absolute Address | 0x00FE940ED0 (CORESIGHT_SOC_ETF_1) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | The Integration Test ATB Master Data Register 0 enables control of the ATDATAM output of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
ITATBMDATA0 (ETF4K) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ATDATAMBit31 | 4 | woWrite-only | 0x0 | Control the value of ATDATAM[31] output of TMC |
| ATDATAMBit23 | 3 | woWrite-only | 0x0 | Control the value of ATDATAM[23] output of TMC |
| ATDATAMBit15 | 2 | woWrite-only | 0x0 | Control the value of ATDATAM[15] output of TMC |
| ATDATAMBit7 | 1 | woWrite-only | 0x0 | Control the value of ATDATAM[7] output of TMC |
| ATDATAMBit0 | 0 | woWrite-only | 0x0 | Control the value of ATDATAM[0] output of TMC |