ITMISCOP0 (ETR) Register Description
Register Name | ITMISCOP0 |
---|---|
Offset Address | 0x0000000EE0 |
Absolute Address | 0x00FE970EE0 (CORESIGHT_SOC_ETR) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | The Integration Test Miscellaneous Output Register 0 controls the values of some outputs from the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
ITMISCOP0 (ETR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
FULL | 1 | woWrite-only | 0x0 | Set the value of the FULL output. |
ACQCOMP | 0 | woWrite-only | 0x0 | Set the value of the ACQCOMP output. |