ITR (R5_DBG_0) Register Description
| Register Name | ITR |
|---|---|
| Offset Address | 0x0000000084 |
| Absolute Address | 0x00FEBF0084 (CORESIGHT_R5_DBG_0) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | Instruction Transfer Register |
ITR (R5_DBG_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Instruction | 31:0 | woWrite-only | 0 | The Instruction Transfer Register, bits [31:0] contain the Arm instruction for the processor to execute while in debug state. Note: Writes to the ITR when the processor is not in debug state or the DSCR[13] execute instruction enable bit is clearedare Unpredictable. When an instruction is issued to the processor, the debug unit prevents the next instruction from being issued until the DSCR[25] instruction complete bit is set. |