ITTRFLIN (ETF8K) Register Description
Register Name | ITTRFLIN |
---|---|
Offset Address | 0x0000000EE8 |
Absolute Address | 0x00FE950EE8 (CORESIGHT_SOC_ETF_2) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | This register returns the values of the FLUSHIN and TRIGIN inputs to the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
ITTRFLIN (ETF8K) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
FLUSHIN | 1 | roRead-only | 0x0 | Read the value of the FLUSHIN input. |
TRIGIN | 0 | roRead-only | 0x0 | Read the value of the TRIGIN input. |