I_MSII_BASE_LO (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

I_MSII_BASE_LO (AXIPCIE_MAIN) Register Description

Register NameI_MSII_BASE_LO
Offset Address0x0000000310
Absolute Address 0x00FD0E0310 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionIngress PCI Express Received MSI Interrupt Translation - Source Address Low

I_MSII_BASE_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
i_msii_base_lo31:12rwNormal read/write0x0This field is recommended to be set to 0xFE440
Reserved11:0roRead-only0x0