I_MSII_CAPABILITIES (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

I_MSII_CAPABILITIES (AXIPCIE_MAIN) Register Description

Register NameI_MSII_CAPABILITIES
Offset Address0x0000000300
Absolute Address 0x00FD0E0300 (AXIPCIE_MAIN)
Width32
TyperoRead-only
Reset Value0x1F0C0001
DescriptionIngress PCI Express Received MSI Interrupt Translation - Capabilities

I_MSII_CAPABILITIES (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
i_msii_size_max31:24roRead-only0x1Fi_msii_size supports values between 0 and i_msii_size_max. Maximum translation size is 2^(i_msii_size_offset+i_msii_size_max).
i_msii_size_offset23:16roRead-only0xCMinimum translation size is 2^(i_msii_size_offset).
Reserved15:1roRead-only0x0
i_msii_present 0roRead-only0x1Translation presence indicator.