I_MSIX_BASE_LO (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

I_MSIX_BASE_LO (AXIPCIE_MAIN) Register Description

Register NameI_MSIX_BASE_LO
Offset Address0x0000000330
Absolute Address 0x00FD0E0330 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionIngress PCI Express Received MSI-X Interrupt Translation - Source Address Low

I_MSIX_BASE_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
i_msix_base_lo31:12rwNormal read/write0x0i_msix_src_base[31:12].
Reserved11:0roRead-only0x0