I_MSIX_CONTROL (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

I_MSIX_CONTROL (AXIPCIE_MAIN) Register Description

Register NameI_MSIX_CONTROL
Offset Address0x0000000328
Absolute Address 0x00FD0E0328 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionIngress PCI Express Received MSI-X Interrupt Translation - Control

I_MSIX_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:21roRead-only0x0
i_msix_size20:16rwNormal read/write0x0Size of this translation window, expressed as 2^(msix_size_offset+msix_size). Constrained by the i_msix_size_max and i_msix_size_offset fields.
Reserved15:1roRead-only0x0
i_msix_enable 0rwNormal read/write0x0Translation Enable. The translation is hit when both of the following are true:
* i_msix_enable == 1
* i_msix_src_base[63:(12+i_msix_size)] == AXI Address[63:(12+i_msix_size)]