LAR (ETR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

LAR (ETR) Register Description

Register NameLAR
Offset Address0x0000000FB0
Absolute Address 0x00FE970FB0 (CORESIGHT_SOC_ETR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionThis is used to enable write access to device registers. External accesses from a debugger (PADDRDBG31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the component.

LAR (ETR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ACCESS_W31:0woWrite-only0A write of 0xC5ACCE55 enables further write access to this device. A write of any value other than 0xC5ACCE55 will have the affect of removing write access.