LOCK (XMPU_DDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

LOCK (XMPU_DDR) Register Description

Register NameLOCK
Offset Address0x0000000020
Absolute Address 0x00FD000020 (DDR_XMPU0_CFG)
0x00FD010020 (DDR_XMPU1_CFG)
0x00FD020020 (DDR_XMPU2_CFG)
0x00FD030020 (DDR_XMPU3_CFG)
0x00FD040020 (DDR_XMPU4_CFG)
0x00FD050020 (DDR_XMPU5_CFG)
Width 1
TyperwNormal read/write
Reset Value0x00000000
DescriptionRegister Write Lock.

All register writes must be done by a secure bus master as defined by TrustZone. The write lock prevents the secure master from writing to all registers except the status registers: ISR, IMR, IEN and IDS. Note: all XMPU registers are readable by secure bus masters. Note: regardless of the LOCK [RegWrDis] setting, the status registers are always writeable by secure and non-secure bus masters.

LOCK (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RegWrDis 0rwNormal read/write0x0Register Write Disable. Applies to all registers except ISR, IMR, IEN and IDS.
0: read/write allowed.
1: read-only.
Once this bit is set, it can only be cleared by an DDR_XMPU reset.