LSR (A53_DBG_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

LSR (A53_DBG_3) Register Description

Register NameLSR
Offset Address0x0000000FB4
Absolute Address 0x00FEF10FB4 (CORESIGHT_A53_DBG_3)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionExternal Debug Lock Status Register

LSR (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
nTT 2roRead-only0Not thirty-two bit access required. RAZ.
SLK 1roRead-only0Software lock status for this component. For an access to LSR that is not a memory-mapped access, or when the software lock is not implemented, this field is RES0.For memory-mapped accesses when the software lock is implemented, possible values of this field are:
SLI 0roRead-only0Software lock implemented. For an access to LSR that is not a memory-mapped access, this field is RAZ. For memory-mapped accesses, the value of this field is IMPLEMENTATION DEFINED. Permitted values are: