LSR (CTI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

LSR (CTI) Register Description

Register NameLSR
Offset Address0x0000000FB4
Absolute Address 0x00FEBF8FB4 (CORESIGHT_R5_CTI_0)
0x00FEBF9FB4 (CORESIGHT_R5_CTI_1)
0x00FE990FB4 (CORESIGHT_SOC_CTI_0)
0x00FE9A0FB4 (CORESIGHT_SOC_CTI_1)
0x00FE9B0FB4 (CORESIGHT_SOC_CTI_2)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionThis indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers, except the Lock Access Register.External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. This register reads as 0 when read from an external debugger (paddrdbg31 = 1).

LSR (CTI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LOCKTYPE 2roRead-only0x0Indicates if the Lock Access Register (0xFB0) is implemented as 8-bit or 32-bit
LOCKGRANT 1roRead-only0x0Returns the current status of the Lock. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers.
LOCKEXIST 0roRead-only0x0Indicates that a lock control mechanism exists for this device. This bit reads as 0 when read from an external debugger (paddrdbg31 = 1) since external debugger accesses are not subject to Lock Registers.