LSR (STM) Register Description
Register Name | LSR |
---|---|
Offset Address | 0x0000000FB4 |
Absolute Address | 0x00FE9C0FB4 (CORESIGHT_SOC_STM) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Status of Lock Control Mechanism. |
Indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. The lock mechanism does not impact accesses to the extended stimulus port registers. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, blocks write accesses to any register, except the STMLAR. The lock mechanism is only present for accesses with the PADDRDBG31 signal LOW.
LSR (STM) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
nTT | 2 | roRead-only | 0x0 | Indicates that the STM implements the 32-bit STMLAR. |
SLK | 1 | roRead-only | 0x0 | Returns the current status of the lock: 0: Access Permitted. 1: Device Locked. |
SLI | 0 | roRead-only | 0x0 | Indicates that a lock control mechanism exists for this device: 1: Lock Present |