LSR (STM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

LSR (STM) Register Description

Register NameLSR
Offset Address0x0000000FB4
Absolute Address 0x00FE9C0FB4 (CORESIGHT_SOC_STM)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionStatus of Lock Control Mechanism.

Indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. The lock mechanism does not impact accesses to the extended stimulus port registers. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, blocks write accesses to any register, except the STMLAR. The lock mechanism is only present for accesses with the PADDRDBG31 signal LOW.

LSR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
nTT 2roRead-only0x0Indicates that the STM implements the 32-bit STMLAR.
SLK 1roRead-only0x0Returns the current status of the lock:
0: Access Permitted.
1: Device Locked.
SLI 0roRead-only0x0Indicates that a lock control mechanism exists for this device:
1: Lock Present