Latency_Regulation_Register_S1 (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Latency_Regulation_Register_S1 (CCI400) Register Description

Register NameLatency_Regulation_Register_S1
Offset Address0x0000002134
Absolute Address 0x00FD6E2134 (CCI_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionLatency_Regulation_Register_S1

Latency_Regulation_Register_S1 (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AR_Scale_Fact10:8rwNormal read/write0x0ARQOS scale factor, power of 2 S1
AW_Scale_Fact 2:0rwNormal read/write0x0AWQOS scale factor, power of 2 S1