MIDR_EL1 (A53_DBG_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIDR_EL1 (A53_DBG_2) Register Description

Register NameMIDR_EL1
Offset Address0x0000000D00
Absolute Address 0x00FEE10D00 (CORESIGHT_A53_DBG_2)
Width32
TyperoRead-only
Reset Value0x410FD032
DescriptionMain ID Register

MIDR_EL1 (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Implementer31:24roRead-only0x41The Implementer code. This field must hold an implementer code that has been assigned by Arm. Assigned codes include the following:Hex representationASCII representationImplementer0x41AArm Limited0x42BBroadcom Corporation0x43CCavium Inc.0x44DDigital Equipment Corporation0x49IInfineon Technologies AG0x4DMMotorola or Freescale Semiconductor Inc.0x4ENNVIDIA Corporation0x50PApplied Micro Circuits Corporation0x51QQualcomm Inc.0x56VMarvell International Ltd.0x69iIntel CorporationArm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.
Variant23:20roRead-only0x0An IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.
Architecture19:16roRead-only0xFThe permitted values of this field are:All other values are reserved.
PartNum15:4roRead-only0xD03An IMPLEMENTATION DEFINED primary part number for the device.On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.
Revision 3:0roRead-only0x2An IMPLEMENTATION DEFINED revision number for the device.