MISC_CTRL (CCI_REG) Register Description
| Register Name | MISC_CTRL |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FD5E0000 (CCI_REG) |
| Width | 1 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Controls for the register block. |
MISC_CTRL (CCI_REG) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| slverr_enable | 0 | rwNormal read/write | 0x0 | By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur. Enable/Disable SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0. |