MODE (SWDT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MODE (SWDT) Register Description

Register NameMODE
Offset Address0x0000000000
Absolute Address 0x00FFCB0000 (CSU_WDT)
0x00FF150000 (SWDT)
0x00FD4D0000 (WDT)
Width24
TypemixedMixed types. See bit-field details.
Reset Value0x000001C2
DescriptionWD zero mode register

MODE (SWDT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ZKEY23:12woWrite-only0x0Zero access key - writes to the zero mode register are only valid if this field is set to 0xABC; this field is write only.
Reserved11:9wazWrite as zero0x0Should be zero (sbz)
IRQLN 8:7rwNormal read/write0x3Interrupt request length - selects the number of
system bus inteface clock cycles (LPD_LSBUS_CLK) during which an interrupt request is held active after it is invoked:
00 = 4
01 = 8
10 = 16
11 = 32
RSTLN 6:4rwNormal read/write0x4Reset length - selects the number of system bus inteface clock cycles (LPD_LSBUS_CLK) during which the internal system reset is held active after it is invoked:
000 = 2
001 = 4
010 = 8
011 = 16
100 = 32
101 = 64
110 = 128 111 = 256
Note: The minimum number of cycles required for an system bus reset is two.
Reserved 3wazWrite as zero0x0Should be zero (sbz)
IRQEN 2rwNormal read/write0x0Interrupt request enable - if set, the watchdog will issue an interrupt request when the counter reaches zero, if WDEN = 1.
RSTEN 1rwNormal read/write0x1Reset enable - if set, the watchdog will issue an internal reset when the counter reaches zero, if WDEN = 1.
WDEN 0rwNormal read/write0x0Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.