MODE (SWDT) Register Description
Register Name | MODE |
---|---|
Offset Address | 0x0000000000 |
Absolute Address |
0x00FFCB0000 (CSU_WDT) 0x00FF150000 (SWDT) 0x00FD4D0000 (WDT) |
Width | 24 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x000001C2 |
Description | WD zero mode register |
MODE (SWDT) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ZKEY | 23:12 | woWrite-only | 0x0 | Zero access key - writes to the zero mode register are only valid if this field is set to 0xABC; this field is write only. |
Reserved | 11:9 | wazWrite as zero | 0x0 | Should be zero (sbz) |
IRQLN | 8:7 | rwNormal read/write | 0x3 | Interrupt request length - selects the number of system bus inteface clock cycles (LPD_LSBUS_CLK) during which an interrupt request is held active after it is invoked: 00 = 4 01 = 8 10 = 16 11 = 32 |
RSTLN | 6:4 | rwNormal read/write | 0x4 | Reset length - selects the number of system bus inteface clock cycles (LPD_LSBUS_CLK) during which the internal system reset is held active after it is invoked: 000 = 2 001 = 4 010 = 8 011 = 16 100 = 32 101 = 64 110 = 128 111 = 256 Note: The minimum number of cycles required for an system bus reset is two. |
Reserved | 3 | wazWrite as zero | 0x0 | Should be zero (sbz) |
IRQEN | 2 | rwNormal read/write | 0x0 | Interrupt request enable - if set, the watchdog will issue an interrupt request when the counter reaches zero, if WDEN = 1. |
RSTEN | 1 | rwNormal read/write | 0x1 | Reset enable - if set, the watchdog will issue an internal reset when the counter reaches zero, if WDEN = 1. |
WDEN | 0 | rwNormal read/write | 0x0 | Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled. |