MON_STATUS (AMS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MON_STATUS (AMS) Register Description

Register NameMON_STATUS
Offset Address0x0000000050
Absolute Address 0x00FFA50050 (AMS_CTRL)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionADC SysMon status.

MON_STATUS (AMS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:24roRead-only0x0reserved
jtag_locked23roRead-only0x0SysMon Invalid Clock Indicator.
0: clocking okay.
1: invalid clock frequency.
The ADC clock frequency must not be less than 1 MHz and not exceed 26 MHz. Also, the ams_ref_clk must not exceed 52 MHz.
busy22roRead-only0x0ADC busy indicator.
0: idle.
1: busy (or calibration is occurring).
This bit will read 1 for an extended period of time during the ADC and sensor calibrations.
channel21:16roRead-only0x0Current sensor channel.
Refer to table in UG1085 for a list of channels.
mon_data15:0roRead-only0x0Value generated by ADC for source selected by the MON_STATUS [channel] field.