MR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MR0 (DDR_PHY) Register Description

Register NameMR0
Offset Address0x0000000180
Absolute Address 0x00FD080180 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000052
DescriptionLPDDR4 Mode Register 0

MR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16roRead-only0x0Reserved. Return zeroes on reads.
RSVD_15_815:8roRead-only0x0Reserved. Return zeroes on reads.
CATR 7rwNormal read/write0x0CA Terminating Rank
RSVD_6_5 6:5rwNormal read/write0x2Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
RZQI 4:3rwNormal read/write0x2Built-in Self-Test for RZQ
RSVD_2_0 2:0rwNormal read/write0x2Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.

Alternate Register MR0_DDR3, reset=0xa52
Alternate Register Field: BL Offset=0 Width=2 read-write
[[*]] Description: Burst Length
Alternate Register Field: CL_2 Offset=2 Width=1 read-write
[[*]] Description: CAS Latency
Alternate Register Field: BT Offset=3 Width=1 read-write
[[*]] Description: Burst Type
Alternate Register Field: CL_6_4 Offset=4 Width=3 read-write
[[*]] Description: CAS Latency
Alternate Register Field: TM Offset=7 Width=1 read-write
[[*]] Description: Operating Mode
Alternate Register Field: DR Offset=8 Width=1 read-write
[[*]] Description: DLL Reset
Alternate Register Field: WR Offset=9 Width=3 read-write
[[*]] Description: Write Recovery and Read to Recharge
Alternate Register Field: PD Offset=12 Width=1 read-write
[[*]] Description: Power-Down Control
Alternate Register Field: RSVD Offset=13 Width=3 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: BL Offset=0 Width=2 read-write
[[*]] Description: Burst Length
Alternate Register Field: CL_2 Offset=2 Width=1 read-write
[[*]] Description: CAS Latency
Alternate Register Field: BT Offset=3 Width=1 read-write
[[*]] Description: Burst Type
Alternate Register Field: CL_6_4 Offset=4 Width=3 read-write
[[*]] Description: CAS Latency
Alternate Register Field: TM Offset=7 Width=1 read-write
[[*]] Description: Operating Mode
Alternate Register Field: DR Offset=8 Width=1 read-write
[[*]] Description: DLL Reset
Alternate Register Field: WR_11_9 Offset=9 Width=3 read-write
[[*]] Description: Write Recovery and Read to Recharge
Alternate Register Field: CL_12 Offset=12 Width=1 read-write
[[*]] Description: CAS Latency
Alternate Register Field: WR_13 Offset=13 Width=1 read-write
[[*]] Description: Write Recovery and Read to Precharge
Alternate Register Field: RSVD Offset=14 Width=2 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.