MR1 (DDR_PHY) Register Description
| Register Name | MR1 |
|---|---|
| Offset Address | 0x0000000184 |
| Absolute Address | 0x00FD080184 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000004 |
| Description | LPDDR4 Mode Register 1 |
MR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| RSVD | 15:8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| RDPST | 7 | rwNormal read/write | 0x0 | Read Postamble Length 0 = RD Post-amble = 0.5*tCK (default) 1 = RD Post-amble = 1.5*tCK |
| nWR | 6:4 | rwNormal read/write | 0x0 | Write-recovery for auto-precharge command: 3'b000 = nWR = 6 (default) 3'b001 = nWR = 10 3'b010 = nWR = 16 3'b011 = nWR = 20 3'b100 = nWR = 24 3'b101 = nWR = 30 3'b110 = nWR = 34 3'b111 = nWR = 40 |
| RDPRE | 3 | rwNormal read/write | 0x0 | Read Preamble Length 0 = RD Pre-amble = Static (default) 1 = RD Pre-amble = Toggle |
| WRPRE | 2 | rwNormal read/write | 0x1 | Write Preamble Length 0 = Reserved 1 = WR Pre-amble = 2*tCK |
| BL | 1:0 | rwNormal read/write | 0x0 | Burst Length 2'b00 = BL=16 Sequential (default) 2'b01 = BL=32 Sequential 2'b10 = BL=16 or 32 Sequential (on-the-fly) 2'b11 = Reserved |
Alternate Register MR1_DDR3, reset=0x4
Alternate Register Field: DE Offset=0 Width=1 read-write
[[*]] Description: DLL Enable/Disable
Alternate Register Field: DIC_1 Offset=1 Width=1 read-write
[[*]] Description: Output Driver Impedance Control
Alternate Register Field: RTT_2 Offset=2 Width=1 read-write
[[*]] Description: On Die Termination
Alternate Register Field: AL Offset=3 Width=2 read-write
[[*]] Description: Posted CAS Additive Latency
Alternate Register Field: DIC_5 Offset=5 Width=1 read-write
[[*]] Description: Output Driver Impedance Control
Alternate Register Field: RTT_6 Offset=6 Width=1 read-write
[[*]] Description: On Die Termination
Alternate Register Field: LEVEL Offset=7 Width=1 read-write
[[*]] Description: Write Leveling Enable
Alternate Register Field: RSVD_8 Offset=8 Width=1 read-write
[[*]] Description: Reserved. This is a JEDEC reserved bit for DDR3 and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RTT_9 Offset=9 Width=1 read-write
[[*]] Description: On Die Termination
Alternate Register Field: RSVD_10 Offset=10 Width=1 read-write
[[*]] Description: Reserved. This is a JEDEC reserved bit for DDR3 and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: TDQS Offset=11 Width=1 read-write
[[*]] Description: Termination Data Strobe
Alternate Register Field: QOFF Offset=12 Width=1 read-write
[[*]] Description: Output Enable/Disable
Alternate Register Field: RSVD_15_13 Offset=13 Width=3 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits for DDR3 and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: DE Offset=0 Width=1 read-write
[[*]] Description: DLL Enable/Disable
Alternate Register Field: DIC Offset=1 Width=2 read-write
[[*]] Description: Output Driver Impedance Control
Alternate Register Field: AL Offset=3 Width=2 read-write
[[*]] Description: Posted CAS Additive Latency
Alternate Register Field: RSVD_6_5 Offset=5 Width=2 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits for DDR4 and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: LEVEL Offset=7 Width=1 read-write
[[*]] Description: Write Leveling Enable
Alternate Register Field: RTT Offset=8 Width=3 read-write
[[*]] Description: On Die Termination
Alternate Register Field: TDQS Offset=11 Width=1 read-write
[[*]] Description: Termination Data Strobe
Alternate Register Field: QOFF Offset=12 Width=1 read-write
[[*]] Description: Output Enable/Disable
Alternate Register Field: RSVD_15_13 Offset=13 Width=3 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits for DDR4 and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: BL Offset=0 Width=3 read-write
[[*]] Description: Burst Length
Alternate Register Field: BT Offset=3 Width=1 read-write
[[*]] Description: Burst Type
Alternate Register Field: WC Offset=4 Width=1 read-write
[[*]] Description: Wrap Control
Alternate Register Field: nWR Offset=5 Width=3 read-write
[[*]] Description: Write Recovery
Alternate Register Field: RSVD Offset=8 Width=8 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits for LPDDR2 and is recommend by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: BL Offset=0 Width=3 read-write
[[*]] Description: Burst Length
Alternate Register Field: BT Offset=3 Width=1 read-write
[[*]] Description: Burst Type
Alternate Register Field: WC Offset=4 Width=1 read-write
[[*]] Description: Wrap Control
Alternate Register Field: nWR Offset=5 Width=3 read-write
[[*]] Description: Write Recovery
Alternate Register Field: RSVD Offset=8 Width=8 read-write
[[*]] Description: Reserved. These are JEDEC reserved bits for LPDDR3 and is recommend by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.