MR12 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MR12 (DDR_PHY) Register Description

Register NameMR12
Offset Address0x00000001B0
Absolute Address 0x00FD0801B0 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x0000004D
DescriptionLPDDR4 Mode Register 12

MR12 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved. Return zeroes on reads.
RSVD 7rwNormal read/write0x0These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
VR_CA 6rwNormal read/write0x1VREF_CA Range Select.
VREF_CA 5:0rwNormal read/write0xDControls the VREF(ca) levels for Frequency-Set-Point[1:0].

Alternate Register MR12_DDR3, reset=0x4d
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.