MR13 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MR13 (DDR_PHY) Register Description

Register NameMR13
Offset Address0x00000001B4
Absolute Address 0x00FD0801B4 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionLPDDR4 Mode Register 13

MR13 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved. Return zeroes on reads.
FSPOP 7rwNormal read/write0x0Frequency Set Point Operation Mode
FSPWR 6rwNormal read/write0x0Frequency Set Point Write Enable
DMD 5rwNormal read/write0x0Data Mask Enable
RRO 4rwNormal read/write0x0Refresh Rate Option
VRCG 3rwNormal read/write0x0VREF Current Generator
VRO 2rwNormal read/write0x0VREF Output
RPT 1rwNormal read/write0x0Read Preamble Training Mode
CBT 0rwNormal read/write0x0Command Bus Training

Alternate Register MR13_DDR3, reset=0x0
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: CBT Offset=0 Width=1 read-write
[[*]] Description: Command Bus Training
Alternate Register Field: RPT Offset=1 Width=1 read-write
[[*]] Description: Read Preamble Training Mode
Alternate Register Field: VRO Offset=2 Width=1 read-write
[[*]] Description: VREF Output
Alternate Register Field: VRCG Offset=3 Width=1 read-write
[[*]] Description: VREF Current Generator
Alternate Register Field: RRO Offset=4 Width=1 read-write
[[*]] Description: Refresh Rate Option
Alternate Register Field: DMD Offset=5 Width=1 read-write
[[*]] Description: Data Mask Enable
Alternate Register Field: FSPWR Offset=6 Width=1 read-write
[[*]] Description: Frequency Set Point Write Enable
Alternate Register Field: FSPOP Offset=7 Width=1 read-write
[[*]] Description: Frequency Set Point Operation Mode
Alternate Register Field: RESERVED_15_8 Offset=8 Width=8 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.