MR2 (DDR_PHY) Register Description
| Register Name | MR2 |
|---|
| Offset Address | 0x0000000188 |
|---|
| Absolute Address |
0x00FD080188 (DDR_PHY)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x00000000 |
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| Description | LPDDR4 Mode Register 2 |
|---|
MR2 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| RSVD | 15:8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| WRL | 7 | rwNormal read/write | 0x0 | Write Leveling |
| WLS | 6 | rwNormal read/write | 0x0 | Write Latency Set |
| WL | 5:3 | rwNormal read/write | 0x0 | Write Latency |
| RL | 2:0 | rwNormal read/write | 0x0 | Read Latency |
Alternate Register MR2_DDR3, reset=0x0
Alternate Register Field: PASR Offset=0 Width=3 read-write
[[*]] Description: Partial Array Self Refresh
Alternate Register Field: CWL Offset=3 Width=3 read-write
[[*]] Description: CAS Write Latency
Alternate Register Field: ASR Offset=6 Width=1 read-write
[[*]] Description: Auto Self-Refresh
Alternate Register Field: SRT Offset=7 Width=1 read-write
[[*]] Description: Self-Refresh Temperature Range
Alternate Register Field: RSVD_8 Offset=8 Width=1 read-write
[[*]] Description: Reserved. This bit is JEDEC reserved and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RTTWR Offset=9 Width=2 read-write
[[*]] Description: Dynamic ODT
Alternate Register Field: RSVD_15_13 Offset=11 Width=5 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: TRR_BAn Offset=0 Width=2 read-write
[[*]] Description: Define which bank (BAn) the target row is located
Alternate Register Field: TRR_BGn_2 Offset=2 Width=1 read-write
[[*]] Description: Define the bank group (BGn) to which TRR will be applied
Alternate Register Field: CWL Offset=3 Width=3 read-write
[[*]] Description: CAS Write Latency
Alternate Register Field: LPASR Offset=6 Width=2 read-write
[[*]] Description: Low Power Array Self Refresh (LP ASR)
Alternate Register Field: TRR_BGn_8 Offset=8 Width=1 read-write
[[*]] Description: Defines the bank group (BGn) to which TRR will be applied
Alternate Register Field: RTTWR Offset=9 Width=3 read-write
[[*]] Description: Dynamic ODT
Alternate Register Field: WRCRC Offset=12 Width=1 read-write
[[*]] Description: Write CRC. When 1b1, CRC is enabled for write operation.
Alternate Register Field: TRR Offset=13 Width=1 read-write
[[*]] Description: TRR Mode setting
Alternate Register Field: RSVD_15_14 Offset=14 Width=2 read-write
[[*]] Description: Reserved. This bit is JEDEC reserved and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RL_WL Offset=0 Width=4 read-write
[[*]] Description: Read and Write Latency
Alternate Register Field: RSVD Offset=4 Width=4 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RSVD1 Offset=8 Width=8 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RL_WL Offset=0 Width=4 read-write
[[*]] Description: Read and Write Latency
Alternate Register Field: WRE Offset=4 Width=1 read-write
[[*]] Description: WR Programming.
Alternate Register Field: RSVD Offset=5 Width=1 read-write
[[*]] Description: This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: WLSEL Offset=6 Width=1 read-write
[[*]] Description: Write Latency Select.
Alternate Register Field: WRL Offset=7 Width=1 read-write
[[*]] Description: Write Leveling.
Alternate Register Field: RSVD1 Offset=8 Width=8 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.