MR4 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MR4 (DDR_PHY) Register Description

Register NameMR4
Offset Address0x0000000190
Absolute Address 0x00FD080190 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionLPDDR4 Mode Register 4

MR4 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8roRead-only0x0Reserved. Return zeroes on reads.
RSVD 7:0rwNormal read/write0x0These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.

Alternate Register MR4_DDR3, reset=0x0
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD_0 Offset=0 Width=1 read-write
[[*]] Description: This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: MPDM Offset=1 Width=1 read-write
[[*]] Description: Maximum Power Down Mode
Alternate Register Field: TCRR Offset=2 Width=1 read-write
[[*]] Description: Temperature Controlled Refresh Range
Alternate Register Field: TCRM Offset=3 Width=1 read-write
[[*]] Description: Temperature Controlled Refresh Mode
Alternate Register Field: IVM Offset=4 Width=1 read-write
[[*]] Description: Internal VREF Monitor
Alternate Register Field: RSVD1 Offset=5 Width=1 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: CS2CMDL Offset=6 Width=3 read-write
[[*]] Description: CS to Command Latency Mode
Alternate Register Field: SRA Offset=9 Width=1 read-write
[[*]] Description: Self Refresh Abort
Alternate Register Field: RPTM Offset=10 Width=1 read-write
[[*]] Description: Read Preamble Training Mode
Alternate Register Field: RDP Offset=11 Width=1 read-write
[[*]] Description: Read Preamble
Alternate Register Field: WRP Offset=12 Width=1 read-write
[[*]] Description: Write Preamble
Alternate Register Field: RSVD_15_13 Offset=13 Width=3 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.