MR4 (DDR_PHY) Register Description
Register Name | MR4 |
Offset Address | 0x0000000190 |
Absolute Address |
0x00FD080190 (DDR_PHY)
|
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | LPDDR4 Mode Register 4 |
MR4 (DDR_PHY) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
Reserved | 31:8 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
RSVD | 7:0 | rwNormal read/write | 0x0 | These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. |
Alternate Register MR4_DDR3, reset=0x0
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD_0 Offset=0 Width=1 read-write
[[*]] Description: This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: MPDM Offset=1 Width=1 read-write
[[*]] Description: Maximum Power Down Mode
Alternate Register Field: TCRR Offset=2 Width=1 read-write
[[*]] Description: Temperature Controlled Refresh Range
Alternate Register Field: TCRM Offset=3 Width=1 read-write
[[*]] Description: Temperature Controlled Refresh Mode
Alternate Register Field: IVM Offset=4 Width=1 read-write
[[*]] Description: Internal VREF Monitor
Alternate Register Field: RSVD1 Offset=5 Width=1 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: CS2CMDL Offset=6 Width=3 read-write
[[*]] Description: CS to Command Latency Mode
Alternate Register Field: SRA Offset=9 Width=1 read-write
[[*]] Description: Self Refresh Abort
Alternate Register Field: RPTM Offset=10 Width=1 read-write
[[*]] Description: Read Preamble Training Mode
Alternate Register Field: RDP Offset=11 Width=1 read-write
[[*]] Description: Read Preamble
Alternate Register Field: WRP Offset=12 Width=1 read-write
[[*]] Description: Write Preamble
Alternate Register Field: RSVD_15_13 Offset=13 Width=3 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.
Alternate Register Field: RSVD Offset=0 Width=16 read-write
[[*]] Description: These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
Alternate Register Field: RESERVED_31_16 Offset=16 Width=16 read-only
[[*]] Description: Reserved. Return zeroes on reads.