MRCTRL0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MRCTRL0 (DDRC) Register Description

Register NameMRCTRL0
Offset Address0x0000000010
Absolute Address 0x00FD070010 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000030
DescriptionMode Register Read/Write Control Register 0.
Note: Do not enable more than one of the following fields simultaneously:
- sw_init_int
- pda_en
- mpr_en

All register fields are dynamic. Dynamic registers can be written at any time during operation.

MRCTRL0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mr_wr31rwNormal read/write0x0Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the DDRC automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
mr_addr15:12rwNormal read/write0x0Address of the mode register that is to be written to.
- 0000 - MR0
- 0001 - MR1
- 0010 - MR2
- 0011 - MR3
- 0100 - MR4
- 0101 - MR5
- 0110 - MR6
- 0111 - MR7
Dont Care for LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPDDR3/LPDDR4)
This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM
In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs.
mr_rank 5:4rwNormal read/write0x3Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually.
Examples (assume DDRC is configured for 2 ranks):
- 0x1 - select rank 0 only
- 0x2 - select rank 1 only
- 0x3 - select ranks 0 and 1
sw_init_int 3rwNormal read/write0x0Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not.
For DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization.
For LPDDR4, this bit can be used to program additional mode registers before automatic SDRAM initialization if necessary.
Note: This must be cleared to 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start.
- 0 - Software intervention is not allowed
- 1 - Software intervention is allowed
pda_en 2rwNormal read/write0x0Indicates whether the mode register operation is MRS in PDA mode or not
- 0 - MRS
- 1 - MRS in Per DRAM Addressability mode
mpr_en 1rwNormal read/write0x0Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4)
- 0 - MRS
- 1 - WR/RD for MPR
mr_type 0rwNormal read/write0x0Indicates whether the mode register operation is read or write. Only used for LPDDR3/LPDDR4/DDR4.
- 0 - Write
- 1 - Read