MRCTRL1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MRCTRL1 (DDRC) Register Description

Register NameMRCTRL1
Offset Address0x0000000014
Absolute Address 0x00FD070014 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMode Register Read/Write Control Register 1

This register is dynamic. Dynamic registers can be written at any time during operation.

MRCTRL1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mr_data17:0rwNormal read/write0x0Mode register write data for all non-LPDDR3/non-LPDDR4 modes.
For LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as
[15:8] MR Address
[7:0] MR data for writes, dont care for reads.