MRCTRL2 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MRCTRL2 (DDRC) Register Description

Register NameMRCTRL2
Offset Address0x000000001C
Absolute Address 0x00FD07001C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMode Register Read/Write Control Register 2

This register is dynamic. Dynamic registers can be written at any time during operation.

MRCTRL2 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
mr_device_sel31:0rwNormal read/write0x0Indicates the device(s) to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to Device 1 etc.
A 1 should be programmed to indicate that the MRS command should be applied to that device.
A 0 indicates that the MRS commands should be skipped for that device.