MRSTAT (DDRC) Register Description
| Register Name | MRSTAT |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address | 0x00FD070018 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Mode Register Read/Write Status Register |
MRSTAT (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| pda_done | 8 | roRead-only | 0x0 | The SoC core may initiate an MR write operation in PDA mode only if this signal is low. This signal goes high when three consecutive MRS commands related to the PDA mode are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to perform PDA operation next time. - 0 - Indicates that mode register write operation related to PDA is in progress or has not started yet. - 1 - Indicates that mode register write operation related to PDA has competed. |
| mr_wr_busy | 0 | roRead-only | 0x0 | The SoC core may initiate an MR write operation only if this signal is low. This signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when MRSTAT.mr_wr_busy is high. - 0 - Indicates that the SoC core can initiate a mode register write operation - 1 - Indicates that mode register write operation is in progress |