MSGF_LEG_MASK (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MSGF_LEG_MASK (AXIPCIE_MAIN) Register Description

Register NameMSGF_LEG_MASK
Offset Address0x0000000424
Absolute Address 0x00FD0E0424 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionLegacy Interrupt Mask.

MSGF_LEG_MASK (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:4roRead-only0x0
msgf_leg_mask_intd 3rwNormal read/write0x0Legacy INTD Interrupt Mask. A Legacy INTD interrupt is generated when msgf_leg_status_intd==1 and msgf_leg_mask_intd==1.
msgf_leg_mask_intc 2rwNormal read/write0x0Legacy INTC Interrupt Mask. A Legacy INTC interrupt is generated when msgf_leg_status_intc==1 and msgf_leg_mask_intc==1.
msgf_leg_mask_intb 1rwNormal read/write0x0Legacy INTB Interrupt Mask. A Legacy INTB interrupt is generated when msgf_leg_status_intb==1 and msgf_leg_mask_intb==1.
msgf_leg_mask_inta 0rwNormal read/write0x0Legacy INTA Interrupt Mask. A Legacy INTA interrupt is generated when msgf_leg_status_inta==1 and msgf_leg_mask_inta==1.