| Field Name | Bits | Type | Reset Value | Description |
|---|
| pcie_core_event_mask | 31:16 | rwNormal read/write | 0x0 | PCI Express Core Event Interrupt[15:0] Mask.
Set bit[i] to 1 to allow interrupts to be generated for PCI Express Core Event[i]. |
| Reserved | 15:8 | roRead-only | 0x0 | |
| egress_address_translation_error_mask | 7 | rwNormal read/write | 0x0 | egress_address_translation_error Interrupt Mask. Set to 1 to allow interrupts to be generated when egress_address_translation_error == 1. |
| ingress_address_translation_error_mask | 6 | rwNormal read/write | 0x0 | ingress_address_translation_error Interrupt Mask. Set to 1 to allow interrupts to be generated when ingress_address_translation_error == 1. |
| master_error_mask | 5 | rwNormal read/write | 0x0 | master_error Interrupt Mask. Set to 1 to allow interrupts to be generated when master_error == 1. |
| slave_error_mask | 4 | rwNormal read/write | 0x0 | slave_error Interrupt Mask. Set to 1 to allow interrupts to be generated when slave_error == 1. |
| uncorrectable_write_error_mask | 3 | rwNormal read/write | 0x0 | uncorrectable_write_error Interrupt Mask. Set to 1 to allow interrupts to be generated when uncorrectable_write_error == 1. |
| Reserved | 2 | roRead-only | 0x0 | |
| rx_msg_overflow_mask | 1 | rwNormal read/write | 0x0 | rx_msg_overflow Interrupt Mask. Set to 1 to allow interrupts to be generated when rx_msg_overflow == 1. |
| rx_msg_avail_mask | 0 | rwNormal read/write | 0x0 | rx_msg_avail Interrupt Mask. Set to 1 to allow interrupts to be generated when rx_msg_avail == 1. |