MSGF_MISC_STATUS (AXIPCIE_MAIN) Register Description
| Register Name | MSGF_MISC_STATUS |
|---|---|
| Offset Address | 0x0000000400 |
| Absolute Address | 0x00FD0E0400 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Received Interrupt and Message Controller - Miscellaneous Interrupt Status. |
MSGF_MISC_STATUS (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| pcie_core_event | 31:16 | wtcReadable, write a 1 to clear | 0x0 | Misc Interrupts from the PCIe Controller [31:27]:Reserved [26]:Link Bandwidth Management Status bit set in Link Status Register. This interrupt is only relevant to Root mode [25]:Link Autonomous Bandwidth Management Status bit set in Link Status Register. This interrupt is only relevant to Root mode [24]:PCIe Link down [23]:Fatal Error Detected bit set in Device Status Register [22]:Non-Fatal Error Detected bit set in Device Status Register [21]:Correctable Error Detected bit set in Device Status Register [20]:UR Detected bit set in Device Status Register [19]:TS1/2 with Hot Reset bit set received from link partner. This interrupt is only relevant to EP mode and should be diabled (masked) when operating as Root [18]:Correctable Error logged in AER Root Error Status register and reporting is enabled [17]:Non-Fatal Error logged in AER Root Error Status register and reporting is enabled [16]:Fatal Error logged in AER Root Error Status register and reporting is enabled |
| Reserved | 15:8 | roRead-only | 0x0 | |
| egress_address_translation_error | 7 | wtcReadable, write a 1 to clear | 0x0 | Egress Address Translation Security Violation. Set to 1 when a Security violation occurs on any Egress Translation. |
| ingress_address_translation_error | 6 | wtcReadable, write a 1 to clear | 0x0 | Ingress Address Translation Security Violation. Set to 1 when a Security violation occurs on any Ingress Translation. |
| master_error | 5 | wtcReadable, write a 1 to clear | 0x0 | AXI Master Error. Set to 1 when a request on the AXI Master Interface is completed with SLVERR or DECERR status. |
| slave_error | 4 | wtcReadable, write a 1 to clear | 0x0 | AXI Slave Error. Set to 1 when a request on the AXI Slave Interface is completed with SLVERR or DECERR status. |
| uncorrectable_write_error | 3 | wtcReadable, write a 1 to clear | 0x0 | Uncorrectable write hardware/software Error. Set to 1 when there is an error detected for a write request to a non-DMA register (from either AXI or PCIe). |
| Reserved | 2 | roRead-only | 0x0 | |
| rx_msg_overflow | 1 | wtcReadable, write a 1 to clear | 0x0 | Received Message FIFO Overflow. Set to 1 whenever a message is attempted to be written into the Received Message FIFO, but the message is discarded because the Received Message FIFO is full. Since there is a finite amount of Received Message FIFO storage space, software should process Received Messages with high priority to keep the Received Message FIFO from becoming full and dropping messages. |
| rx_msg_avail | 0 | wtcReadable, write a 1 to clear | 0x0 | Received Message FIFO Available. Set to 1 whenever the Received Message FIFO becomes not empty. Message contents are available on the msgf_rx_fifo_type/msg/address_lo/address_hi/data ports. |