MSGF_MSI_MASK_LO (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MSGF_MSI_MASK_LO (AXIPCIE_MAIN) Register Description

Register NameMSGF_MSI_MASK_LO
Offset Address0x0000000448
Absolute Address 0x00FD0E0448 (AXIPCIE_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMSI Interrupt Mask[31:0].

MSGF_MSI_MASK_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
msgf_msi_mask31:0rwNormal read/write0x0An interrupt is generated on the int_msi[0] output port when (msgf_msi_status[31:0] & msgf_msi_mask[31:0]) != 0.