MSR_0 (APMDDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MSR_0 (APMDDR) Register Description

Register NameMSR_0
Offset Address0x0000000044
Absolute Address 0x00FD0B0044 (APM_DDR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMetric Selector, Counters 0, 1, 2, and 3

Slot Selections: 000: DDR slave port 0. 001: DDR slave port 1. 010: DDR slave port 2. 011: DDR slave port 3. 100: DDR slave port 4. 101: DDR slave port 5. others: reserved. Metric Selections: Refer to UG1085, Interconnect Chapter.

MSR_0 (APMDDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MET_CT3_SLOT31:29rwNormal read/write0x0Counter 3 slot select.
MET_CT3_SEL28:24rwNormal read/write0x0Counter 3 metric select.
MET_CT2_SLOT23:21rwNormal read/write0x0Counter 2 slot select.
MET_CT2_SEL20:16rwNormal read/write0x0Counter 2 metric select.
MET_CT1_SLOT15:13rwNormal read/write0x0Counter 1 slot select.
MET_CT1_SEL12:8rwNormal read/write0x0Counter 1 metric select.
MET_CT0_SLOT 7:5rwNormal read/write0x0Counter 0 slot select.
MET_CT0_SEL 4:0rwNormal read/write0x0Counter 0 metric select.