MSTR (DDRC) Register Description
| Register Name | MSTR |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address | 0x00FD070000 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x03040001 |
| Description | Master Register |
All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.
MSTR (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| device_config | 31:30 | rwNormal read/write | 0x0 | Indicates the configuration of the device used in the system. - 00 - Reserved - 01 - x8 device - 10 - x16 device - 11 - x32 device |
| frequency_mode | 29 | rwNormal read/write | 0x0 | Choose which registers are used. - 0 - Original registers - 1 - Shadow registers |
| active_ranks | 25:24 | rwNormal read/write | 0x3 | Each bit represents one rank. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - One rank - 11 - Two ranks - Others - Reserved. |
| burst_rdwr | 19:16 | rwNormal read/write | 0x4 | SDRAM burst length used: - 0001 - Reserved - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for LPDDR4) All other values are reserved. This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100). |
| dll_off_mode | 15 | rwNormal read/write | 0x0 | Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and this bit must be set to 0. Programming Mode: Quasi-dynamic Group 2 |
| data_bus_width | 13:12 | rwNormal read/write | 0x0 | Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that quarter bus width mode is only supported for DDR4. Bus width refers to DQ bus width (excluding any ECC width). |
| en_2t_timing_mode | 10 | rwNormal read/write | 0x0 | If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in LPDDR3/LPDDR4 mode. |
| lpddr4 | 5 | rwNormal read/write | 0x0 | Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use |
| ddr4 | 4 | rwNormal read/write | 0x0 | Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use |
| lpddr3 | 3 | rwNormal read/write | 0x0 | Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use |
| ddr3 | 0 | rwNormal read/write | 0x1 | Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use |