ODTCFG_SHADOW (DDRC) Register Description
| Register Name | ODTCFG_SHADOW |
|---|---|
| Offset Address | 0x0000002240 |
| Absolute Address | 0x00FD072240 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x04000400 |
| Description | ODT Configuration Shadow Register |
This register is quasi-dynamic group 1 and group 4. Group 1 registers can be written when no read/write traffic is present at the DFI. Group 4 registers can be written depending on MSTR.frequency_mode.
ODTCFG_SHADOW (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| wr_odt_hold | 27:24 | rwNormal read/write | 0x4 | Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) |
| wr_odt_delay | 20:16 | rwNormal read/write | 0x0 | The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) |
| rd_odt_hold | 11:8 | rwNormal read/write | 0x4 | Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK) |
| rd_odt_delay | 6:2 | rwNormal read/write | 0x0 | The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the DDRC. Recommended values: DDR3: - CL - CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) |