ODTCR (DDR_PHY) Register Description
| Register Name | ODTCR |
|---|---|
| Offset Address | 0x0000000098 |
| Absolute Address | 0x00FD080098 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00010000 |
| Description | ODT Configuration Register |
ODTCR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | roRead-only | 0x0 | Reserved; Do not change from default value. |
| WRODT_RSVD | 27:18 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| WRODT | 17:16 | rwNormal read/write | 0x1 | Write ODT: Specifies whether ODT should be enabled (1b1) or disabled (1b0) on each of the up to 2 ranks when a write command is sent to rank n, n=0 to 1. Each rank has its own 2-bit WRDODT field which is indirectly accessed using RANKIDR register. The 2 bits of the field each represent a rank, the LSB being rank 0 and the MSB being rank 1. Default is to enable ODT only on rank being written to. The default shown in this register is for rank 0 - the default for the other ranks will have the nth bit set where n corresponds to the number of the rank. |
| Reserved | 15:12 | roRead-only | 0x0 | Reserved. Return zeroes on reads. |
| RDODT_RSVD | 11:2 | roRead-only | 0x0 | Reserved. Return zeroes on reads |
| RDODT | 1:0 | rwNormal read/write | 0x0 | Read ODT: Specifies whether ODT should be enabled (1b1) or disabled (1b0) on each of the up to 2 ranks when a read command is sent to rank n, n=0 to 1. Each rank has its own 2-bit RDODT field which is indirectly accessed using RANKIDR register. The 2 bits of the field each represent a rank, the LSB being rank 0 and the MSB being rank 1. Default is to disable ODT during reads. |