OVSSET_EL0 (A53_PMU_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

OVSSET_EL0 (A53_PMU_1) Register Description

Register NameOVSSET_EL0
Offset Address0x0000000CC0
Absolute Address 0x00FED30CC0 (CORESIGHT_A53_PMU_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Overflow Flag Status Set Register

OVSSET_EL0 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
C31rwNormal read/write0x0PMCCNTR_EL0 overflow bit.
P30:0rwNormal read/write0x0Event counter overflow set bit for EVCNTR<x>.N is the value in PMCR_EL0.N. Bits [30:N] are RAZ/WI.Possible values are: