PATGEN_CRC_G (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PATGEN_CRC_G (DISPLAY_PORT) Register Description

Register NamePATGEN_CRC_G
Offset Address0x000000CC14
Absolute Address 0x00FD4ACC14 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
Description16 bit CRC calculated on the second component of video output from Internal Test Pattern Generator

PATGEN_CRC_G (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:16razRead as zero0x0
CRC_G15:0roRead-only0x0