PATTERN_GEN_SELECT (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PATTERN_GEN_SELECT (DISPLAY_PORT) Register Description

Register NamePATTERN_GEN_SELECT
Offset Address0x000000B100
Absolute Address 0x00FD4AB100 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPATTERN_GEN_SELECT:PATTERN_GEN_SELECT:

PATTERN_GEN_SELECT (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
OFFSET_EQ31:8rwNormal read/write0x0Depends on audio sample rate: Need to program an offset value which is needed by audio pattern generator to generate ping pattern (250ms)
2B11h: 44.1 KHz
2EE0h: 48 KHz
Reserved 7:2razRead as zero0x0
AUD_RATE_SEL 1:0rwNormal read/write0x0Bits[1:0] - Audio Pattern generator
1: 44.1 KHz
2: 48 KHz