PCCFG (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PCCFG (DDRC) Register Description

Register NamePCCFG
Offset Address0x0000000400
Absolute Address 0x00FD070400 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort Common Configuration Register

This register is static. Static registers can only be written when the controller is in reset.

PCCFG (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
bl_exp_mode 8rwNormal read/write0x0Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit.
This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect.
This can be used in cases where Partial Writes is enabled and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd_mw penalty in LPDDR4.
Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases:
- MSTR.reg_ddrc_data_bus_width=01 and MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only)
Functionality is also not supported if Shared-AC is enabled
pagematch_limit 4rwNormal read/write0x0Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled.
If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions.
go2critical_en 0rwNormal read/write0x0If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on
urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b0.