PCFGQOS0_0 (DDRC) Register Description
| Register Name | PCFGQOS0_0 |
|---|---|
| Offset Address | 0x0000000494 |
| Absolute Address | 0x00FD070494 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Port 0 Read QoS Configuration Register 0 |
This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.
PCFGQOS0_0 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| rqos_map_region1 | 21:20 | rwNormal read/write | 0x0 | This bitfield indicates the traffic class of region 1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. |
| rqos_map_region0 | 17:16 | rwNormal read/write | 0x0 | This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. |
| rqos_map_level1 | 3:0 | rwNormal read/write | 0x0 | Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. |