PCIE_REF_CTRL (CRF_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PCIE_REF_CTRL (CRF_APB) Register Description

Register NamePCIE_REF_CTRL
Offset Address0x00000000B4
Absolute Address 0x00FD1A00B4 (CRF_APB)
Width32
TyperwNormal read/write
Reset Value0x00001500
DescriptionPCIe Clock Generator Control.

PCIE_REF_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25rwNormal read/write0x0reserved
CLKACT24rwNormal read/write0x0Clock active control.
0: disable. Clock stop.
1: enable.
Reserved23:14rwNormal read/write0x0reserved
DIVISOR013:8rwNormal read/write0x156-bit divider.
Reserved 7:3rwNormal read/write0x0reserved
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL_TO_FPD
010: RPLL_TO_FPD
011: DPLL