PCTRL_3 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PCTRL_3 (DDRC) Register Description

Register NamePCTRL_3
Offset Address0x00000006A0
Absolute Address 0x00FD0706A0 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort 3 Control Register

This register is dynamic. Dynamic registers can be written at any time during operation.

PCTRL_3 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
port_en 0rwNormal read/write0x0Enables port 3.