PDCR (A53_ETM_0) Register Description
Register Name | PDCR |
---|---|
Offset Address | 0x0000000310 |
Absolute Address | 0x00FEC40310 (CORESIGHT_A53_ETM_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Power Down Control Register |
PDCR (A53_ETM_0) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
PU | 3 | rwNormal read/write | 0x0 | Powerup request bit: Typically, a trace unit drives a signal representing the value of this bit to a power controller to request that the trace unit core power domain is powered up. However, if the trace unit and the processor are in the same power domain then the implementation might combine the PU status with a signal from the processor. |