PDCR (A53_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PDCR (A53_ETM_0) Register Description

Register NamePDCR
Offset Address0x0000000310
Absolute Address 0x00FEC40310 (CORESIGHT_A53_ETM_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPower Down Control Register

PDCR (A53_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PU 3rwNormal read/write0x0Powerup request bit: Typically, a trace unit drives a signal representing the value of this bit to a power controller to request that the trace unit core power domain is powered up. However, if the trace unit and the processor are in the same power domain then the implementation might combine the PU status with a signal from the processor.