PDSR (A53_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PDSR (A53_ETM_0) Register Description

Register NamePDSR
Offset Address0x0000000314
Absolute Address 0x00FEC40314 (CORESIGHT_A53_ETM_0)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPower Down Status Register

PDSR (A53_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
LOCKED 5roRead-only0OS Lock status bit: The value is UNKNOWN when the trace unit core power domain is powered down, that is, when POWER==0.
STICKYPD 1roRead-only0Sticky powerdown status bit. Indicates whether the trace register state is valid:After this register is read, if the Software Lock is unlocked and the trace unit core power domain is powered up, then the trace unit sets this bit to 0. The
controls whether the Software Lock is locked.
POWER 0roRead-only0Power status bit