PDSR (A53_ETM_1) Register Description
Register Name | PDSR |
---|---|
Offset Address | 0x0000000314 |
Absolute Address | 0x00FED40314 (CORESIGHT_A53_ETM_1) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | Power Down Status Register |
PDSR (A53_ETM_1) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
LOCKED | 5 | roRead-only | 0 | OS Lock status bit: The value is UNKNOWN when the trace unit core power domain is powered down, that is, when POWER==0. |
STICKYPD | 1 | roRead-only | 0 | Sticky powerdown status bit. Indicates whether the trace register state is valid:After this register is read, if the Software Lock is unlocked and the trace unit core power domain is powered up, then the trace unit sets this bit to 0. The controls whether the Software Lock is locked. |
POWER | 0 | roRead-only | 0 | Power status bit |